Dp 397 en

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Connection of fast serial communication bus to PowerPC processor[edit]

Author: Hrouda Michal

Diplomové práce 2010

Download thesis in PDF

This diploma thesis describes method for FPGA configuration by peripheral of Power PC processor, its connection to processor external memory bus. For tests of previous tasks, the test application in PikeOS system have been written. This application communicates via FPGA with modules connected by PIRANHA serial bus.

Dp 2010 hrouda michal.pdf